The goal of the Seventh International Workshop on Automatic Performance Tuning (iWAPT2012) is to bring together researchers who are investigating automated techniques for constructing and/or adapting algorithms and software for high-performance on modern complex machine architectures.
This year, are soliciting two kinds of contributions: regular papers and previously published papers. Only regular papers will become a part of the formal proceedings, though all papers will be distributed to workshop attendees. The goal of this format is to encourage broad participation in the workshop, both for new work and prior but current work. All accepted papers will be assigned a speaking slot in the workshop's agenda.
Regular papers present new, previously unpublished work. Such papers will undergo the usual peer-review, judged on the criteria of novelty, technical soundness, and writing quality. If accepted, they become part of the official VECPAR proceedings. They will also be included in the post-conference proceedings of VECPAR 2012, which Springer will publish in the Lecture Notes in Computer Science series. Publication is subject to confirmation by the iWAPT program committee that the authors have revised the paper per reviewer comments as needed. Further information about the process will be sent to authors with the notice of acceptance.
Prior papers are those that have already been published but still reflect the authors' current interests. They may also be new surveys of the authors' prior work. Importantly, such papers will be distributed locally to attendees but will not be included in the formal published proceedings. Review of such papers will be lighter, with acceptance determined by availability of time in the program, relevance, and likely significance to workshop attendees.
In the context of automatic generation of linear algebra algorithms, it is not uncommon to find dozens of algorithmic variants, all equivalent mathematically, but different in terms of accuracy and performance. In this talk I discuss how to rank the variants automatically, without executing them. In principle, one can attempt a fully analytical approach, creating performance models that take into account both the structure of the algorithm and the features of the processor; unfortunately, due to the intricacies of the memory system, currently this solution is not at all systematic. By contrast, I present an approach based on the automatic modeling of the routines that represent the building blocks for linear algebra algorithms. Performance predictions are then made by composing evaluations of such models. Our experiments show how this approach can be applied to both algorithm ranking and parameter tuning, yielding remarkably accurate results.
Paolo Bientinesi studied Computer Science at the University of Pisa (1998, MS) and at the University of Texas at Austin (2006, PhD). Since 2008 he is Junior Professor in "Algorithm & Code Generation for High-Performance Architectures" at RWTH Aachen (Germany). He is the deputy director of the Aachen Institute for Computational Engineering Science (AICES), where leads the group "High-Performance and Automatic Computing" (www.hpac.rwth-aachen.de). In 2009 he was awarded the Karl Arnold Prize of the North Rhine-Westphalian Academy of Sciences and Humanities, given for outstanding research work of a young scientist.
Hardware accelerators hold tremendous promise for the future of computational science at extreme scales. They also represent a formidable challenge to the developers of performance-optimized numerical kernels, due to the complexity of resource scheduling under in the presence of massive concurrency. Hand tuning numerical kernels for such devices is unfeasible, while autotuning is both generally applicable and highly sustainable. This talk presents promising results of using classic heuristic autotuning approaches to produce fast matrix multiplication kernels for NVIDIA Fermi (Tesla 2050) and Kepler (GTX 680) systems, and how the methodology is being shaped into an extensible software framework.
Jakub Kurzak received the MSc degree in Electrical and Computer Engineering from Wroclaw University of Technology, Poland, and the PhD degree in Computer Science from the University of Houston. He is a Research Director in the Innovative Computing Laboratory, Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville. His research interests include parallel algorithms, specifically in the area of numerical linear algebra, and also parallel programming models and performance optimization for multicore processors and hardware accelerators.
Please follow the guidelines for VECPAR 2012, which is in the LNCS format. Regular papers must not exceed 15 pages for the main text, with any number of additional pages for references. (That is, references do not count against the 15 page limit.) Prior papers may be submitted in the format of the original publication.
Also, please indicate how you wish your paper to be considered as a subtitle of your submission. For prior papers, also indicate where the paper appeared previously.
Submission must be made through the web form. See: http://iwapt.org/2012/submit
| Full papers submission due: |
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| Notification of acceptance of papers: | |
| Camera ready papers: | |
| Conference sessions: | Tuesday July 17th, 2012 |
To join the workshop, you must register for VECPAR2012.
The registration page for VECPAR2012 will be found at http://nkl.cc.u-tokyo.ac.jp/VECPAR2012/
Richard Vuduc, Georgia Institute of Technology, USA
Takeshi Iwashita, Kyoto University, Japan
Toshiyuki Imamura, The University of Electro-communications, Japan
Akira Naruse, Fujitsu Laboratories Ltd., Japan
Franz Franchetti, Carnegie Mellon University, USA
Takahiro Katagiri, University of Tokyo, Japan
Osni Marques, Lawrence Berkeley National Laboratory, USA
David Padua, University of Illinois Urbana Champaign, USA
Markus Püschel, ETH Zurich, Switzerland
Takao Sakurai, Hitachi Ltd, Japan
Hiroyuki Takizawa, Tohoku University, Japan
Keita Teranishi, Cray, USA
Yusaku Yamamoto, Kobe University, Japan
Masahiro Yasugi, Kyoto University, Japan
| General Chair: | Hiroyuki Takizawa, Tohoku University, Japan |
| Finance Chair: | Toshiyuki Imamura, The University of Electro-communication, Japan |
| SC liaison: | Reiji Suda, The University of Tokyo, Japan |
| Web Chair: | Hisayasu Kuroda, Ehime University, Japan |
| Publicity Chair: | Akihiro Fujii, Kogakuin University, Japan |
| Local Arrangement: | Takaharu Yaguchi, Kobe University, Japan |
| PC Chair: | Richard Vuduc, Georgia Institute of Technology, USA |
Victor Eijkhout, Texas Advanced Computing Center, University of Texas, USA
Toshiyuki Imamura, The University of Electro-Communications, Japan
Domingo Jimenez Canovas, University of Murcia, Spain
Takahiro Katagiri, The University of Tokyo, Japan
Ken Naono, Hitachi Ltd., Japan
Osni A. Marques, Lawrence Berkley National Laboratory, USA
Markus Püschel, ETH Zurich, Switzerland
Reiji Suda, The University of Tokyo, Japan
Richard Vuduc, Georgia Institute of Technology, USA
R. Clint Whaley, University of Texas at San Antonio, USA
Yusaku Yamamoto, Kobe University, Japan
Jonathan T. Carter, NERSC/Lawrence Berkley National Laboratory, USA
John Cavazos, University of Delaware, USA
iWAPT2012 Organizing Committee
E-mail: iWAPT2012-oc_at_sc.isc.tohoku.ac.jp (replace "_at_" by "@" in the email address)